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Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Low thermal resistance
g
PSMN025-100D
QUICK REFERENCE DATA
d
SYMBOL
VDSS = 100 V ID = 47 A RDS(ON) 25 m
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:* d.c. to d.c. converters * switched mode power supplies The PSMN025-100D is supplied in the SOT428 (Dpak) surface mounting package.
PINNING
PIN 1 2 3 tab gate drain1 source DESCRIPTION
SOT428 (DPAK)
tab
2
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 100 100 20 47 33 188 150 175 UNIT V V V A A A W C
1 It is not possible to make connection to pin 2 of the SOT428 package. August 1999 1 Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 40 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 10 V; refer to fig:15
PSMN025-100D
MIN. -
MAX. 260
UNIT mJ
IAS
-
47
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT428 package, pcb mounted, minimum footprint TYP. MAX. UNIT 50 1 K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C Drain-source on-state VGS = 10 V; ID = 25 A resistance Gate source leakage current VGS = 10 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance Tj = 175C Tj = 175C MIN. 100 89 2 1 TYP. MAX. UNIT 3 22 0.02 0.05 61 13 25 18 72 69 58 3.5 7.5 2600 340 195 4 6 25 68 100 10 500 V V V V V m m nA A A nC nC nC ns ns ns ns nH nH pF pF pF
ID = 45 A; VDD = 80 V; VGS = 10 V
VDD = 50 V; RD = 1.8 ; VGS = 10 V; RG = 5.6 Resistive load Measured tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS
PSMN025-100D
MIN. -
TYP. MAX. UNIT 0.87 82 0.26 47 188 1.2 A A V ns C
IF = 25 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V
-
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PSMN025-100D
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
1
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
0.1
0.1 0.05 0.02
0.01 single pulse
P D
tp
D = tp/T
T
0.001 1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 10V 35 30 25 20 15 10 5 4V 4.4 V 4.2 V 1.8 2 5V 4.8 V 4.6 V 8V 6V Tj = 25 C
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
40
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); VGS 10 V
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
1000
0.16 RDS(on) = VDS/ ID 100 tp = 10 us 100 us 10 D.C. 1 1 ms 10 ms 100 ms 0.04 0.14 0.12 0.1 0.08 0.06
Drain-Source On Resistance, RDS(on) (Ohms) 4.2 V 4V 4.4 V 4.6 V 4.8 V Tj = 25 C
5V
8V 0.02 0.1 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 0 2 4 6 8 10 12 Drain Current, ID (A) 14 16 18
6V
VGS = 10V 20
Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PSMN025-100D
Drain current, ID (A) 50 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 Gate-source voltage, VGS (V) 175 C Tj = 25 C VDS > ID X RDS(ON)
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
Threshold Voltage, VGS(TO) (V) maximum typical
minimum
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Transconductance, gfs (S) 50 45 40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 Drain current, ID (A) 40 45 50 175 C VDS > ID X RDS(ON) Tj = 25 C
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1.0E-01
Drain current, ID (A)
1.0E-02 minimum typical 1.0E-04 maximum 1.0E-05
1.0E-03
1.0E-06 0 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C
Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss
100
Crss
10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PSMN025-100D
Maximum Avalanche Current, IAS (A)
Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 45A Tj = 25 C VDD = 20 V
100
25 C
VDD = 80 V
10
Tj prior to avalanche = 150 C
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Gate charge, QG (nC)
1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
Source-Drain Diode Current, IF (A) 50 45 40 35 30 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) 175 C Tj = 25 C VGS = 0 V
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped)
PSMN025-100D
SOT428
seating plane y A E b2 A A1 mounting base A2 D1
E1 D HE L2
2
L L1
1
b1 e e1 b
3
wM A c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) 0.65 0.45 A2 0.89 0.71 b 0.89 0.71 b1 max. 1.1 0.9 b2 5.36 5.26 c 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 HE max. 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.7 0.5 w 0.2 y max. 0.2
2.285 4.57
Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
PSMN025-100D
7.0
2.15 2.5
1.5
4.57
Fig.17. SOT428 : soldering pattern for surface mounting.
August 1999
8
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PSMN025-100D
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
9
Rev 1.000

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